1. Field of the Invention
The present invention relates to a non-volatile memory device and a non-volatile memory cell which can non-volatilely store information even during power-off, and particularly to a fast accessible non-volatile memory device and a fast accessible non-volatile memory cell. More particularly, the present invention relates to a structure for non-volatilizing stored information during power-off in a semiconductor memory device in which memory cells include flip-flop circuits as components.
2. Description of the Background Art
As a semiconductor device implementing non-volatile storage of information, there has been known a read-only memory (ROM). Among known types of ROMs, a mask ROM stores information by fixedly writing it with a masked interconnection, and an EPROM stores information by electrically writing it. As electrically erasable and programmable memory (EEPROM), there has been known a "flash memory" in which each memory cell is formed of one floating gate type transistor.
FIGS. 54A and 54B schematically show a structure of a memory cell of a conventional flash memory and a sectional structure of the cell, respectively. In FIG. 54A, a memory cell MT is formed of a floating gate type transistor 900 having a floating gate FG for storing electric charges, one conduction terminal connected to a bit line BL, a control gate CD connected to a word line WL and another conduction terminal connected to a source line SL. Although FIG. 54A representatively shows only one memory cell, control gates CG of a plurality of memory cells MT arranged in one row are connected to word line WL, and a plurality of memory cells MT (more specifically, the one conduction terminal of each of transistors 900) arranged in one column are connected to bit line BL.
In FIG. 54B, memory cell MT includes high concentration impurity regions 912 and 914 formed at a surface of a semiconductor substrate 910 (or a well), floating gate FG formed on a region between impurity regions 921 and 914 with a gate insulating film 916 laid therebetween, and control gate CG formed on floating gate FG with an interlayer insulating film 918 interposed therebetween. High concentration impurity region 912 functions as a source region, and is connected to a source line SL. High concentration impurity region 914 functions as a drain region, and is connected to bit line BL. Memory transistor 900 has a threshold voltage which varies depending on a quantity of charges (electrons) existing in floating gate FG. The magnitude of this threshold voltage is made corresponding to "0" or "1". Injection of charges (electrons) into floating gate FG and removal of charges (electrons) from floating gate FG are performed as follows.
When charges are to be injected into the floating gate, a high voltage Vpp, e.g., of about 12 V is applied to control gate CG, and a high voltage Vp, e.g., of about 7 V which is somewhat higher than a normal power supply voltage Vcc is applied to drain region 914 as shown in FIG. 55. A ground potential of 0 V is applied to source region 912 and substrate (well) region 910. In this state, a channel region of a low resistance is formed between drain region 914 and source region 912. Electrons e flow from source region 912 into drain region 914. A high intensity electric field is generated at drain region 914 by the relatively large voltage between the source and drain, and electrons e are excited to be hot electrons by this high electric field at the vicinity of the drain region. Avalanche breakdown increases the quantity of hot electrons generated by the high electric field at the vicinity of the drain region, and the hot electrons near the channel region and drain region 914 are accelerated by the high electric field across control gate CG and substrate region 910 to be supplied into and accumulated in floating gate FG. In the state that a large amount of electrons e are accumulated in floating gate FG, threshold voltage Vth of transistor 900 measured with respect to control gate CG increases.
When electrons are to be removed from floating gate FG, a high voltage Vpa, e.g., of 10 V is applied to source region 912, and drain region 914 is set to an electrical floating state as shown in FIG. 56. The ground potential (0 V) is applied to control gate CG and substrate region 910. In this state, a high voltage between source region 912 and control gate CG is capacitance-divided to be applied across a region between source region 912 and floating gate FG. Owing to the high electric field between source region 912 and floating gate FG, a Fowler-Nordheim tunneling current flows from source region 912 into floating gate FG, so that electrons e stored in floating gate FG flow into source region 912 and electrons are removed from floating gate FG. When electrons accumulated in floating gate FG decreases in quantity, threshold voltage Vth of transistor measured with respect to control gate CG decreases.
More specifically, threshold voltage Vth goes to a value of Vth1 as can be seen from a relationship represented by line I in FIG. 57, when the electrons have been removed from the floating gate. Also, threshold voltage Vth goes to a value of Vth2 and a relationship between the voltage applied to control gate and current between source and drain is represented by a line II when the electrons have been injected into the floating gate.
In the normal operation, i.e., in the data reading operation, the source region is fixed to the ground potential. In a memory cell selecting operation, a predetermined voltage, e.g., at power supply voltage Vcc level is applied to word line WL. The voltage applied to the selected word line is at a level between threshold voltages Vth1 and Vth2. Therefore, the floating gate type transistor is turned on or maintains the off state depending on the quantity of electrons accumulated in the floating gate. The floating gate type transistor maintains the off state even when it is selected, if electrons have been injected into the floating gate and thus the threshold voltage is increased. In this case, a current does not flow through the bit line. Meanwhile, when the floating gate type transistor has a reduced threshold voltage due to removal of electrons from the floating gate, the floating gate type transistor is turned on when selected, and a current flows through the bit line. Data is determined depending on whether the current flows through the bit line or not.
Detection of the current flowing through the bit line is performed by a sense amplifier of a current sense type. The sense amplifier of the current sense type generally converts a current into a voltage, and compares the converted voltage with a reference voltage Vref for reading data. Therefore, as compared with a structure in which a differential amplifier differentially amplifies potentials of signal lines transmitting complementary signals, a long time is required for reading data because voltage change appearing on one data line is sensed, and thus data cannot be read at a high speed.
As a fast accessible semiconductor memory device, there has been known an SRAM (Static Random Access Memory). An SRAM cell includes a flip-flop circuit as a component, as shown in FIG. 59.
In FIG. 59, the SRAM cell is provided corresponding to a crossing between a word line WL and a bit line pair BL and /BL. The SRAM cell includes N-channel MOS transistors 920a and 920b which form the flip-flop circuit and have their gates and drains cross-coupled together, access transistors 922a and 922b which connect storage nodes 923a and 923b to bit lines BL and /BL, respectively, and load elements Z1 and Z2 for pulling up potentials of storage nodes 923a and 923b. Load elements Z1 and Z2 may be formed of resistor elements of a high resistance made of, e.g., polycrystalline silicon, or may be formed of p-channel MOS transistor having a relatively large on-resistance, a thin film transistor or the like.
The flip-flop circuit formed of transistors 920a and 920b latches signal potentials at storage nodes 923a and 923b.
For writing/reading data, the signal potential on word line WL rises to the potential of "H" indicative of the selected state, access transistors 922a and 922b are turned on, and storage nodes 923a and 923b are connected to bit lines BL and /BL. For reading data, the potentials of bit lines BL and /BL change in accordance with the signal potentials held at storage nodes 923a and 923b, and the differential amplifier amplifies the potential difference between bit lines BL and /BL, whereby data is read. For writing data, signal potentials, which correspond to write-data and are logically complementary to each other, are transmitted onto bit lines BL and /BL, and these logically complementary signals corresponding to the write data are transmitted to storage nodes 923a and 923b and latched thereat.
As shown in FIG. 59, the SRAM cell has six elements, and thus is formed of more components than a memory cell, e.g., of an ROM formed of one transistor, resulting in disadvantageous increase of manufacturing cost. However, the storage data is latched by the flip-flop (transistors 920a and 920b), so that the stored information is stably held as long as the power is on, and it is not necessary to perform refreshing which is required, e.g., in a DRAM (Dynamic Random Access Memory) for holding the stored information. Also, a complicated timing control is not required for accessing, and the operation timings can be controlled relatively easily. Further, there are provided paired complementary transmission lines, i.e., bit lines BL and /BL, and the signal potentials on these paired complementary bit lines are differentially amplified, so that a fast operation is implemented. The power supply voltage is applied to storage nodes 223a and 223b of memory cell via load elements Z1 and Z2 of high resistance, and the power consumption of memory cell during a standby state is extremely small, so that backup of the stored information can be performed with a battery (DRAM must perform the refreshing for holding the stored information even during the standby, so that the power consumption thereof is large).
The SRAM having the foregoing advantage, however, loses all the stored information when the power is cut off. Thus, the SRAM shown in FIG. 59 cannot non-volatilely store the information. Therefore, an SRAM with non-volatile storage of information has been proposed.
FIG. 60 shows a structure of a cell of the conventional SRAM having a non-volatile data storage function. In FIG. 60, the non-volatile SRAM includes n-channel MOS transistors QB and QC forming a flip-flop, access transistors QA and QD which are turned on to connect storage nodes A and B to bit lines BL and /BL in response to a signal potential on word line WL, respectively, and floating gate type transistors QF1 and QF2 connected between storage nodes A and B and power potential supply node VC, respectively. Each of floating gate type transistors QF1 and QF2 has a control gate and a drain connected together to a power potential supply node VC. Both floating gate type transistors QF1 and QF2 are kept on and function as load elements during the normal operation (writing and reading of data). In the normal operation, when the signal potential on word line WL attains "H", storage nodes A and B are connected to bit lines BL and /BL, respectively, so that writing or reading of data is performed. Non-volatile storage of data is performed as follows.
The potential of word line WL is set to "L". It is assumed that the potential of storage node A is "H", and the potential of storage node B is "L". The signal potentials of storage nodes A and B are the power supply potential VC level and the ground potential level. In this state, voltage VC applied to power potential supply node VC is raised to a value not lower than a pinch-off voltage of transistors QF1 and QF2. Since the potentials of storage nodes A and B are "H" and "L", respectively, transistor QC is on and transistor QB is off. Therefore, a current does not flow through the floating gate type transistor QF1 regardless of the potential of power voltage supply node VC. Accordingly, the threshold voltage of transistor QF1 does not change.
Meanwhile, a current flows through transistor QF2. Therefore, when the potential of this power voltage supply node VC increases to or above the pinch-off voltage, avalanche breakdown occurs owing to a high drain electric field in transistor QF2, and thus hot electrons are injected into its floating gate, so that the threshold voltage of transistor QF2 increases. Owing to the change of threshold voltages of transistors QF1 and QF2, data "1" is non-volatilely written. The threshold voltages of transistors QF1 and QF2 depend on the quantities of electric charges (electrons) stored in their floating gates, and thus do not change even when the power voltage at power voltage supply node VC is cut off.
When the power supply voltage is supplied to power voltage supply node VC, transistor QF1 is turned on prior to turn-on of transistor QF2, because the threshold voltage of transistor QF1 is lower than that of transistor QF2. Therefore, the potential of storage node A increases above the potential of storage node B, so that transistor QC is turned on prior to turn-on of transistor QB, and the 5 signal potentials of storage nodes A and B are latched by transistors QB and QC forming the flip-flop. Thus, non-volatile data "1" already written is reproduced.
The threshold voltages of transistors QF1 and QF2 are returned to the initial state by ultraviolet ray radiation.
According to the structure of the non-volatile SRAM in the prior art, the floating gates and drains of the floating gate type transistors are connected to the same voltage supply node. A voltage not lower than the pinch-off voltage is applied to the drain to cause the avalanche breakdown for generating hot electrons. Although the avalanche breakdown occurs also at the channel region, hot electrons are generated substantially at the vicinity of the drain region, because a high voltage is applied between the channel and the drain in the pinch-off state. The hot electrons thus generated must be accelerated with a sufficiently large accelerating voltage in order to inject the hot electrons into the floating gate. However, a potential difference is not caused if the same voltage is applied to the control gate and the drain region. Therefore, the hot electrons generated near the drain region cannot be sufficiently accelerated toward the floating gate, and thus the electrons cannot be efficiently injected into the floating gate. In this case, the generated hot electrons are trapped in a gate insulating film, which may impair the reliability of the gate insulating film.
Since the floating gate type transistor is essentially an N-channel MOS transistor of an enhancement type, its current supply capability is set small for achieving a function as a load element. Therefore, the channel current (drain current) is small, and the number of hot electrons generated therein are small. Accordingly, if electrons cannot be injected into the floating gate with a high efficiency, a sufficient amount of electrons cannot be injected into the floating gate, so that necessary and sufficient change of the threshold voltage cannot be caused in the floating gate type transistor, resulting in a problem that reliable non-volatile storage of data is impossible.
Ultraviolet ray radiation is performed for emitting electrons from the floating gate. For this ultraviolet ray radiation, a semiconductor memory device must be accommodated in an expensive package having an ultraviolet ray transparent window, resulting in increase of a cost of the semiconductor memory device.